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3.3v 16k/32k x 36 flex36? synchronous dual-port static ram cy7c09569v cy7c09579v cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 document #: 38-06054 rev. ** revised september 7, 2001 25/0251 features ? true dual-ported memory cells which allow simulta- neous access of the same memory location two flow-through/pipelined devices ? 16k x 36 organization (cy7c09569v) ? 32k x 36 organization (cy7c09579v) 0.25-micron cmos for optimum speed/power three modes ? flow-through ? pipelined ?burst bus-matching capabilities on right port (x36 to x18 or x9) byte-select capabilities on left port 100-mhz pipelined operation high-speed clock to data access 5/6/8 ns 3.3v low operating power ? active = 250 ma (typical) ? standby = 10 a (typical) fully synchronous interface for ease of use burst counters increment addresses internally ? shorten cycle times ? minimize bus noise ? supported in flow-through and pipelined modes counter address read back via i/o lines single chip enable automatic power-down commercial and industrial temperature ranges compact package ? 144-pin tqfp (20 x 20 x 1.4 mm) ? 172-ball bga (1.0-mm pitch) (15 x 15 x 0.51 mm) note: 1. a 0 ? a 13 for 16k; a 0 ? a 14 for 32k devices. logic block diagram r/w l b 0 ? b 3 oe l ft /pipe l i/o 18l ? i/o 26l a 0 ? a 13/14l clk l ads l cnten l cntrst l a 0 ? a 13/14r clk r ads r cnten r cntrst r counter/ address register decode true dual-ported ram array counter/ address register decode 9 [1] [1] 14/15 14/15 i/o 27l ? i/o 35l 9 i/o 0l ? i/o 8l 9 i/o 9l ? i/o 17l 9 ce l i/o control left port control logic r/w r oe r ft /pipe r 9 9 i/o r 9 9 ce r i/o control right port control logic bus match 9/18/36 bm size be for the most recent information, visit the cypress web site at www.cypress.com
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 2 of 30 functional description the cy7c09569v and cy7c09579v are high-speed 3.3v synchronous cmos 16k and 32k x 36 dual-port static rams. two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. regis- ters on control, address, and data lines allow for minimal set- up and hold times. in pipelined output mode, data is registered for decreased cycle time. clock to data valid t cd2 = 5 ns (pipe- lined). flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. in flow- through mode data will be available t cd1 = 12.5 ns after the address is clocked into the device. pipelined output or flow- through mode is selected via the ft /pipe pin. each port contains a burst counter on the input address regis- ter. the internal write pulse width is independent of the exter- nal r/w low duration. the internal write pulse is self-timed to allow the shortest possible cycle times. a high on ce for one clock cycle will power down the internal circuitry to reduce the static power consumption. in the pipe- lined mode, one cycle is required with ce low to reactivate the outputs. counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. a port ? s burst counter is loaded with the port ? s address strobe (ads ). when the port ? s count enable (cnten ) is asserted, the address counter will increment on each low-to-high transition of that port ? s clock signal. this will read/write one word from/into each successive address location until cnten is deasserted. the counter can address the entire memory array and will loop back to the start. counter reset (cntrst ) is used to reset the burst counter. all parts are available in 144-pin thin quad plastic flatpack (tqfp) and 172-ball ball grid array (bga) packages.
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 3 of 30 pin configurations notes: 2. this pin is a14l for cy7c09579v. 3. this pin is a14r for cy7c09579v. 144-pin thin quad flatpack (tqfp) top view i/o32l i/o33r i/o23l i/o33l 2 3 4 i/o34l i/o34r 5 i/o35l i/o35r 6 a0l a0r 7 a1l a1r 8 a2l a2r 9 a3l a3r 10 a4l a4r 11 a5l a5r 12 a6l a6r 13 a7l 108 a7r 14 b0 107 bm 15 b1 106 size 16 b2 105 be 17 b3 104 vss 18 oel 103 oer 19 r/wl 102 r/wr 20 vdd 101 vdd 21 vss 100 vss 22 vss 99 vss 23 cel 98 cer 24 clkl 97 clkr 25 adsl 96 adsr 26 cntrstl 95 cntrstr 27 cntenl 94 cntenr 28 ft /pipel 93 ft /piper 29 a8l 92 a8r 30 a9l 91 a9r 31 a10l 90 a10r 32 a11l 89 a11r 33 a12l 88 a12r 34 a13l 87 a13r 35 nc 86 nc 36 i/o26l 85 i/o26r i/o25l 84 i/o25r i/o24l 83 i/o24r 82 81 41 42 43 44 i/o22l i/o31l 45 vss vss 46 i/o21l i/o30l 47 i/o20l i/o29l 48 i/o19l i/o28l 49 i/o18l i/o27l 50 vdd vdd 51 i/o8l i/o17l 52 i/o7l i/o16l 53 i/o6l i/o15l 54 i/o5l i/o14l 55 vss vss 56 i/o4l i/o13l 57 i/o3l i/o12l 58 i/o2l 143 i/o11l 59 i/o1l 142 i/o10l 60 i/o0l 141 i/o9l 61 i/o0r 140 i/o9r 62 i/o1r 139 i/o10r 63 i/o2r 138 i/o11r 64 i/o3r 137 i/o12r 65 i/o4r 136 i/o13r 66 vss 135 vss 67 i/o5r 134 i/o14r 68 i/o6r 133 i/o15r 69 i/o7r 132 i/o16r 70 i/o8r 131 i/o17r 71 vdd 130 vdd 72 i/o18r 129 i/o27r 123 i/o19r 128 i/o28r 122 i/o20r 127 i/o29r 121 i/o21r 126 i/o30r 120 vss 125 vss 119 i/o22r 124 i/o31r 118 i/o23r i/o32r 117 116 37 38 39 40 80 79 78 77 76 75 74 73 115 114 113 112 111 110 109 144 1 cy7c09569v (16k x 36) cy7c09579v (32k x 36) [2] [3]
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 4 of 30 pin configurations (continued) 172-ball ball grid array (bga) top view 1234567891011121314 a i/o32l i/o30l nc vss i/o13l vdd i/o11l i/o11r vdd i/o13r vss nc i/o30r i/o32r b a0l i/o33l i/o29 i/o17l i/o14l i/o12l i/o9l i/o9r i/o12r i/o14r i/o17r i/o29r i/o33r a0r c nc a1l i/o31l i/o27l nc i/o15l i/o10l i/o10r i/o15r nc i/o27r i/o31r a1r nc d a2l a3l i/o35l i/o34l i/o28l i/o16l vss vss i/o16r i/o28r i/o34r i/o35r a3r a2r e a4l a5l nc b0l nc nc nc nc bm nc a5r a4r f vdd a6l a7l b1l nc nc size a7r a6r vdd g oel b2l b3l cel cer vss be oer h vss r/w la8lclkl clkr a8r r/w rvss j a9l a10l vss adsl nc nc adsr vss a10r a9r k a11l a12l nc cntrstl nc nc nc nc cntrstr nc a12r a11r l ft /pipel a13l cntenl i/o26l i/o25l i/o19l vss vss i/o19r i/o25r i/o26r cntenr a13r ft /piper m nc nc [2] i/o22l i/o18l nc i/o7l i/o2l i/o2r i/o7r nc i/o18r i/o22r nc [3] nc n i/o24l i/o20l i/o8l i/o6l i/o5l i/o3l i/o0l i/o0r i/3r i/o5r i/o6r i/o8r i/o20r i/o24r p i/o23l i/o21l nc vss i/o4l vdd i/o1l i/o1r vdd i/o4r vss nc i/o21r i/o23r
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 5 of 30 selection guide cy7c09569v cy7c09579v -100 cy7c09569v cy7c09579v -83 cy7c09569v cy7c09579v -67 f max2 (mhz) (pipelined) 100 83 67 max. access time (ns) (clock to data, pipelined) 5 6 8 typical operating current i cc (ma) 250 240 230 typical standby current for i sb1 (ma) (both ports ttl level) 30 25 25 typical standby current for i sb3 ( a) (both ports cmos level) 10 a10 a 10 a pin definitions left port right port description a 0l ? a 13/14l a 0r ? a 13/14r address inputs (a 0 ? a 13 for 16k, a 0 ? a 14 for 32k devices). ads l ads r address strobe input. used as an address qualifier. this signal should be asserted low to assert the part using the externally supplied address on address pins. to load this address into the burst address counter both ads and cnten have to be low. ads is disabled if cntrst is asserted low ce l ce r chip enable input. clk l clk r clock signal. this input can be free-running or strobed. maximum clock input rate is f max . cnten l cnten r counter enable input. asserting this signal low increments the burst address counter of its respective port on each rising edge of clk. cnten is disabled if cntrst is asserted low. cntrst l cntrst r counter reset input. asserting this signal low resets the burst address counter of its respec- tive port to zero. cntrst is not disabled by asserting ads or cnten . i/o 0l ? i/o 35l i/o 0r ? i/o 35r data bus input/output. oe l oe r output enable input. this signal must be asserted low to enable the i/o data pins during read operations. r/w l r/w r read/write enable input. this signal is asserted low to write to the dual port memory array. for read operations, assert this pin high. ft /pipe l ft /pipe r flow-through/pipelined select input. for flow-through mode operation, assert this pin low. for pipelined mode operation, assert this pin high. b 0l ? b 3l byte select inputs. asserting these signals enable read and write operations to the correspond- ing bytes of the memory array. bm, size select pins for bus matching. see bus matching for details. be big endian pin. see bus matching for details. v ss ground input. v dd power input.
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 6 of 30 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied............................................. ? 55 c to +125 c supply voltage to ground potential ............... ? 0.5v to +4.6v dc voltage applied to outputs in high z state ........................... ? 0.5v to v dd +0.5v dc input voltage................................... ? 0.5v to v dd +0.5v [4] output current into outputs (low)............................. 20 ma static discharge voltage ........................................... >2001v latch-up current..................................................... >200 ma note: 4. pulse width < 20 ns. operating range range ambient temperature v dd commercial 0 c to +70 c 3.3v 165 mv industrial ? 40 c to +85 c 3.3v 165 mv electrical characteristics over the operating range parameter description cy7c09569v cy7c09579v unit -100 -83 -67 min. typ. max. min. typ. max. min. typ. max. v oh output high voltage (v dd = min., i oh = ? 4.0 ma) 2.4 2.4 2.4 v v ol output low voltage (v dd = min., i ol = +4.0 ma) 0.4 0.4 0.4 v v ih input high voltage 2.0 2.0 2.0 v v il input low voltage 0.8 0.8 0.8 v i oz output leakage current ? 10 10 ? 10 10 ? 10 10 a i cc operating current (v dd = max., i out = 0 ma) outputs disabled commercial 250 385 240 360 230 340 ma industrial 270 385 ma i sb1 standby current (both ports ttl level) ce l & ce r v ih , f = f max commercial 30 75 25 70 25 65 ma industrial 35 85 ma i sb2 standby current (one port ttl level) ce l | ce r v ih , f = f max commercial 170 220 160 210 150 200 ma industrial 170 235 ma i sb3 standby current (both ports cmos level) ce l & ce r v dd ? 0.2v, f = 0 commercial 0.01 1 0.01 1 0.01 1 ma industrial 0.01 1 ma i sb4 standby current (one port cmos level) ce l | ce r v ih , f = f max commercial 150 200 140 190 130 180 ma industrial 150 200 ma capacitance parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3v 10 pf c out output capacitance 10 pf
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 7 of 30 notes: 5. external ac test load capacitance = 10 pf. 6. (internal i/o pad capacitance = 10 pf) + ac test load. ac test load and waveforms v th =1.5v output c (a) normal load (load 1) r = 50 ? z 0 = 50 ? [5] 3.0v v ss 90% 90% 10% 3ns 3 ns 10% all input pulses 3.3v output c = 5 pf (b) three-state delay (load 2) r2 = 435 ? r1 = 590 ? (b) load derating curve 1 2 3 4 5 6 7 30 60 80 100 200 ? for t cd2 (ns) capacitance (pf) 20 [6]
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 8 of 30 switching characteristics over the operating range parameter description cy7c09569v cy7c09579v unit -100 -83 -67 min. max. min. max. min. max. f max1 f max flow-through 67 45 40 mhz f max2 f max pipelined 100 83 67 mhz t cyc1 clock cycle time - flow-through 15 22 25 ns t cyc2 clock cycle time - pipelined 10 12 15 ns t ch1 clock high time - flow-through 6.5 7.5 8.5 ns t cl1 clock low time - flow-through 6.5 7.5 8.5 ns t ch2 clock high time - pipelined 4 5 6.5 ns t cl2 clock low time - pipelined 4 5 6.5 ns t r clock rise time 3 3 3 ns t f clock fall time 3 3 3 ns t sa address set-up time 3.5 4 4 ns t ha address hold time 0.5 0.5 0.5 ns t sb byte select set-up time 3.5 4 4 ns t hb byte select hold time 0.5 0.5 0.5 ns t sc chip enable set-up time 3.5 4 4 ns t hc chip enable hold time 0.5 0.5 0.5 ns t sw r/w set-up time 3.5 4 4 ns t hw r/w hold time 0.5 0.5 0.5 ns t sd input data set-up time 3.5 4 4 ns t hd input data hold time 0.5 0.5 0.5 ns t sad ads set-up time 3.5 4 4 ns t had ads hold time 0.5 0.5 0.5 ns t scn cnten set-up time 3.5 4 4 ns t hcn cnten hold time 0.5 0.5 0.5 ns t srst cntrst set-up time 3.5 4 4 ns t hrst cntrst hold time 0.5 0.5 0.5 ns t oe output enable to data valid 8 9 10 ns t olz [7, 8] oe to low z 2 2 2 ns t ohz [7, 8] oe to high z 1 7 1 7 1 7 ns t cd1 clock to data valid - flow-through 12.5 18 20 ns t cd2 clock to data valid - pipelined 5 6 8 ns t ca1 clock to counter address valid - flow-through 12.5 18 20 ns t ca2 clock to counter address valid - pipelined 9 10 11 ns t dc data output hold after clock high 2 2 2 ns t ckhz [7, 8] clock high to output high z 2 6 2 7 2 8 ns t cklz [7, 8] clock high to output low z 2 2 2 ns notes: 7. this parameter is guaranteed by design, but it is not production tested. 8. test conditions used are load 2.
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 9 of 30 port to port delays t cwdd write port clock high to read data delay 30 35 35 ns t ccs clock to clock set-up time 9 10 12 ns switching characteristics over the operating range (continued) parameter description cy7c09569v cy7c09579v unit -100 -83 -67 min. max. min. max. min. max.
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 10 of 30 switching waveforms read cycle for flow-through output (ft /pipe = v il ) [9, 10, 11, 12] read cycle for pipelined operation (ft /pipe = v ih ) [9, 10, 11, 12] notes: 9. oe is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 10. ads = v il , cnten = v il and cntrst = v ih . 11. the output is disabled (high-impedance state) by ce =v ih following the next rising edge of the clock. 12. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk. numbers are for reference only. t ch1 t cl1 t cyc1 t sc t hc t dc t ohz t oe t sc t hc t sw t hw t sa t ha t cd1 t ckhz t dc t olz t cklz a n a n+1 a n+2 a n+3 q n q n+1 q n+2 clk ce r/w address data out oe t sb t hb b 0-3 t ch2 t cl2 t cyc2 t sc t hc t sw t hw t sa t ha a n a n+1 clk ce r/w address data out oe a n+2 a n+3 t sc t hc t ohz t oe t olz t dc t cd2 t cklz q n q n+1 q n+2 1 latency t sb t hb b 0-3
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 11 of 30 bus match read cycle for flow-through output (ft /pipe = v il ) [9, 11, 13, 14, 15] bus match read cycle for pipelined operation (ft /pipe = v ih ) [9, 11, 13, 14, 15] notes: 13. timing shown is for x18 bus matching; x9 bus matching is similar with 4 cycles between address inputs. 14. see table ? right port operation ? for data output on first and subsequent cycles. 15. cnten = v il . in x9 and x18 bus matching burst mode operations (write or read), ads can toggle on the rising edge of every clock cycle or it can be at v ih level all the time except when loading the initial external address (i.e. ads = v il only required when reading or writing the first byte or word). switching waveforms (continued) t ch1 t cl1 t cyc1 t dc t sc t hc t sw t hw t sa t ha t dc t cklz a n a n a n+1 a n+1 q n q n q n+1 clk ce r/w address data out oe low q n+1 1st cycle 1st cycle 2nd cycle 2nd cycle t cd1 ads t ch2 clk ce r/w address data out oe a n a n a n+1 a n+1 q n q n+1 q n t cyc2 t cl2 t sc t hc t sw t hw t sa t ha 1 latency t cd2 t clkz low 1st cycle 2nd cycle 1st cycle t cd2 t cd2 t dc t dc t dc ads
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 12 of 30 bank select pipelined read [16, 17] left port write to flow-through right port read [17, 18, 19, 20, 21] notes: 16. in this depth expansion example, b1 represents bank #1 and b2 is bank #2; each bank consists of one cypress dual-port device from this data sheet. address (b1) = address (b2) . 17. b0 = b1 = b2 = b3 = bm = size = ads = cnten = v il , cntrst = v ih . 18. the same waveforms apply for a right port write to flow-through left port read. 19. ce = b0 = b1 = b2 = b3 = ads = cnten =v il ; cntrst = v ih . 20. oe = v il for the right port, which is being read from. oe = v ih for the left port, which is being written to. 21. if t ccs maximum specified, then data from right port read is not valid until the maximum specified for t cwdd . if t ccs >maximum specified, then data is not valid until t ccs + t cd1 (t cwdd does not apply in this case). switching waveforms (continued) q 3 q 1 q 0 q 2 a 0 a 1 a 2 a 3 a 4 a 5 q 4 a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha t sc t hc t sa t ha t sc t hc t sc t hc t sc t hc t ckhz t dc t dc t cd2 t cklz t cd2 t cd2 t ckhz t cklz t cd2 t ckhz t cklz t cd2 t ch2 t cl2 t cyc2 clk l address (b1) ce (b1) data out(b2) data out(b1) address (b2) ce (b2) t sa t ha t sw t hw t sd t hd match valid t ccs t sw t hw t dc t cwdd t cd1 match t sa t ha match no match no valid valid t dc t cd1 clk l r/w l address l data inl address r data outr clk r r/w r
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 13 of 30 pipelined read-to-write-to-read (oe = v il ) [12, 22, 23, 24] notes: 22. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 23. ce = ads = cnten = v il ; cntrst = v ih . 24. during ? no operation, ? data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. switching waveforms (continued) t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa t hw t sw t cd2 t ckhz t sd t hd t cklz t cd2 no operation write read read clk ce r/w address data in data out a n a n+1 a n+2 a n+2 d n+2 a n+3 a n+4 q n q n+3
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 14 of 30 pipelined read-to-write-to-read (oe controlled) [11, 22, 23, 24] switching waveforms (continued) t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa a n a n+1 a n+2 a n+3 a n+4 a n+5 t hw t sw t sd t hd d n+2 t cd2 t ohz read read write d n+3 t cklz t cd2 q n q n+4 clk ce r/w address data in data out oe
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 15 of 30 bus match pipelined read-to-write-to-read (oe = v il ) [11, 13, 14, 15, 23, 24, 25] note: 25. bm, size, and be must be reconfigured 1 cycle before operation is guaranteed. bm, size, and be should remain static for any particular port configuration. switching waveforms (continued) clk ce r/w address data in data out a n a n a n+1 a n+1 a n+2 a n+2 a n+3 a n+3 a n+4 a n+4 q n q n q n+3 q n+3 d n+2 d n+2 1st word 2nd word 1st word 2nd word 1st word 2nd word t ch2 t cyc2 t cl2 t sc t hc t sw t hw t sa t ha read read read read read read no operation 1st cycle 2nd cycle 1st cycle 2nd cycle write write 1st cycle 2nd cycle t cd2 t cd2 t ckhz t cklz t cd2 t dc t sd t hd ads
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 16 of 30 flow-through read-to-write-to-read (oe = v il ) [10, 12, 13, 14, 23, 24] flow-through read-to-write-to-read (oe controlled) [10 , 12, 22, 23, 24] switching waveforms (continued) t ch1 t cl1 t cyc1 t sw t hw t sa t ha t sw t hw t sd t hd a n a n+1 a n+2 a n+2 a n+3 a n+4 d n+2 q n q n+1 q n+3 t cd1 t cd1 t dc t ckhz t cd1 t cd1 t cklz t dc read no operation write read clk ce address r/w data in data out q n t ch1 t cl1 t cyc1 t sw t hw t sa t ha t cd1 t dc t ohz read a n a n+1 a n+2 a n+3 a n+4 a n+5 d n+2 d n+3 t sw t hw t sd t hd t cd1 t cd1 t cklz t dc q n+4 t oe write read clk ce address r/w data in data out oe
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 17 of 30 bus match flow-through read-to-write-to-read (oe = v il ) [11, 13, 14, 15, 23, 24, 25] switching waveforms (continued) clk ce r/w address a n a n a n+1 a n+1 a n+1 a n+1 a n+1 a n+2 data out data in q n q n q n+1 q n+1 d n+1 d n+1 t ch1 t cl1 t cyc1 t hc t sc t hw t sw t ha t sa t hw t sw 1st word 2nd word t hd t sd 1st word 2nd word 1st cycle 2nd cycle 1st cycle 2nd cycle 1st cycle 2nd cycle read read write write read read no operation t cd1 t cd1 t dc t ckhz t cd1 t cd1 t cklz t dc ads
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 18 of 30 pipelined read with address counter advance [26] flow-through read with address counter advance [26] note: 26. ce = oe = v il ; r/w = cntrst = v ih . switching waveforms (continued) counter hold read with counter t sa t ha t sad t had t scn t hcn t ch2 t cl2 t cyc2 t sad t had t scn t hcn q x ? 1 q x q n q n+1 q n+2 q n+3 t dc t cd2 read with counter read external address clk address ads data out cnten a n t dc t ch1 t cl1 t cyc1 t sa t ha t sad t had t scn t hcn q x q n q n+1 q n+2 a n t sad t had t dc t cd1 counter hold read with counter read external address clk address ads data out cnten q n+4 t scn t hcn t cd1 q n+3 t dc read with counter t cd1
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 19 of 30 write with address counter advance (flow-through or pipelined outputs) [27, 28] notes: 27. ce = b0 = b1 = b2 = b3 = r/w = v il ; cntrst = v ih . 28. the ? internal address ? is equal to the ? external address ? when ads = cnten = v il and cntrst =v ih . switching waveforms (continued) t ch2 t cl2 t cyc2 a n a n+1 a n+2 a n+3 a n+4 d n+1 d n+1 d n+2 d n+3 d n+4 a n d n t sad t had t scn t hcn t sd t hd write external write with counter address write with counter write counter hold clk address internal cnten ads data in address t sa t ha
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 20 of 30 counter reset (pipelined outputs) [11, 22, 29, 30, 31] notes: 29. ce = b0 = b1 = b2 = b3 = v il . 30. no dead cycle exists during counter reset. a read or write cycle may be coincidental with the counter reset. 31. output state (high, low, or high-impedance) is determined by the previous cycle control signals. ideally, data out should be in the high-impedance state during a valid write cycle. switching waveforms (continued) clk address internal cnten ads data in address cntrst r/w data out a n a m a p a x 0 1 a n a m a p q 1 q n q 0 d 0 t ch2 t cl2 t cyc2 t sa t ha t sw t hw t srst t hrst t sd t hd t cd2 t cd2 t cklz [31] reset address 0 counter write read address 0 address 1 read read address a n address a m read
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 21 of 30 counter reset (flow-through outputs) [22, 24, 29, 30, 31] switching waveforms (continued) t ch2 t cl2 t cyc2 clk address internal cnten ads data in address cntrst r/w data out q 0 q 1 d 0 a x 0 1 a n a n+1 t srst t hrst t sd t hd t sw t hw a n a n+1 t sa t ha counter reset write address 0 read address 0 read address 1 read address n q n t cd1
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 22 of 30 pipelined read of state of address counter [32, 33, 34] flow-through read of state of address counter [32, 33, 35] notes: 32. ce = oe = v il ; r/w = cntrst = v ih . 33. when reading address out in x9 bus match mode, readout of a n is extended by 1 cycle. 34. for pipelined address counter read, signals from address counter operation table from must be valid for 2 consecutive cycles for x36 and x18 mode and for 3 consecutive cycles for x9 mode. 35. for flow-through address counter read, signals from address counter operation table must be valid for consecutive cycles for x36. switching waveforms (continued) cnten clk t ch2 t cl2 t cyc2 address ads a n q x-2 q x-1 q n a n q n+1 q n+2 t sa t ha t sad t had t scn t hcn t scn t hcn t scn t hcn t sad t had load address external counter hold read with counter t ca2 internal address a n+1 a n+2 a n read with counter t dc read counter address data out cnten clk t ch1 t cl1 address ads a n q x q n a n q n+1 q n+2 t sa t ha t sad t had t scn t hcn t scn t hcn t scn t hcn t sad t had load external t cyc1 address counter hold read with counter q n+3 t dc t ca1 internal address a n a n+1 a n+2 a n+3 data out read counter address read with counter
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 23 of 30 read/write and enable operation [36, 37, 38] inputs outputs oe clk ce r/w i/o 0 ? i/o 35 operation x h x high-z deselected [39] x l l d in write l l h d out read [39] h x l x high-z outputs disabled address counter control operation [36, 40] address previous address clk oe r/w ads cnten cntrst mode operation x x x x x x l reset counter reset a n x x x l l h load address load into counter a n a n l h l h h hold + read external address blocked - counter address readout x a n x x h h h hold external address blocked - counter disabled x a n x x h l h incre- ment counter increment notes: 36. ? x ? = ? don ? t care, ? ? h ? = v ih , ? l ? = v il . 37. ads , cnten , cntrst = ? don ? t care. ? 38. oe is an asynchronous input signal. 39. when ce changes state in the pipelined mode, deselection and read happen in the following clock cycle. 40. counter operation is independent of ce .
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 24 of 30 right port configuration [25, 41] right port operation [42] readout of internal address counter [43] bm size configuration i/o pins used 0 0 x36 i/o 0r ? 35r 1 0 x18 i/o 0r ? 17r 11 x9 i/o 0r ? 8r configuration be data on 1st cycle data on 2nd cycle data on 3rd cycle data on 4th cycle x18 0 dq 0r ? 17r dq 18r ? 35r -- x18 1 dq 18r ? 35r dq 0r ? 17r -- x9 0 dq 0r ? 8r dq 9r ? 17r dq 18r ? 26r dq 27r ? 35r x9 1 dq 27r ? 35r dq 18r ? 26r dq 9r ? 17r dq 0r ? 8r configuration address on 1st cycle i/o pins used on 1st cycle address on 2nd cycle i/o pins used on 2nd cycle left port x36 a 0l ? 14l i/o 3l ? 17l -- right port x36 a 0r ? 14r i/o 3r ? 17r -- right port x18 wa, a 0r ? 14r i/o 2r ? 17r -- right port x9 a 6r ? 14r i/o 0r ? 8r ba, wa, a 0r ? 5r i/o 1r ? 8r left port operation control pin effect b0 i/o 0 ? 8 byte control b1 i/o 9 ? 17 byte control b2 i/o 18 ? 26 byte control b3 i/o 27 ? 35 byte control notes: 41. in x36 mode, be input is a ? don ? t care. ? 42. dq represents data output of the chip. 43. x18 and x9 configuration apply to right port only.
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 25 of 30 counter operation the cy7c09569v/09579v dual-port ram (dpram) con- tains on-chip address counters (one for each port) for the syn- chronous members of the product family. besides the main x36 format, the right port allows bus matching (x18 or x9, user- selectable). an internal sub-counter provides the extra ad- dresses required to sequence out the 36-bit word in 18-bit or 9-bit increments. the sub-counter counts up in the ? little en- dian ? mode, and counts down if the user has chosen the ? big endian ? mode. the address counter is required to be in incre- ment mode in order for the sub-counter to sequence out the second word (in x18 mode) or the remaining three bytes (in x9 mode). for a x36 format (the only active format on the left port), each address counter in the cy7c09579v uses addresses (a 0 ? 14 ). for the right port (allowing for the bus-matching feature), a maximum of two address bits (out of a 2-bit sub-counter) are added. 1. ads l/r (pin #23/86) is a port ? s address strobe, allowing the loading of that port ? s burst counters if the corresponding cnten l/r pin is active as well. 2. cnten l/r (pin #25/84) is a port ? s count enable, provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications; when asserted, the ad- dress counter will increment on each positive transition of that port ? s clock signal. 3. cntrst l/r (pin #24/85) is a port ? s burst counter reset. a new read-back (hold+read mode) feature has been added, which is different between the left and right port due to the bus matching feature provided only for the right port. in read-back mode the internal address of the counter will be read from the data i/os as shown in figure 1 . bus match operation the right port of the cy7c09569v/09579v 16k/32kx36 dual- port sram can be configured in a 36-bit long-word, 18-bit word, or 9-bit byte format for data i/o. the data lines are divid- ed into four lanes, each consisting of 9 bits (byte-size data lines). the bus match select (bm) pin works with bus size select (size) and big endian select (be) to select the bus width (long-word, word, or byte) and data sequencing arrangement for the right port of the dual-port device. a logic ? 0 ? applied to both the bus match select (bm) pin and to the bus size select (size) pin will select long-word (36-bit) operation. a logic ? 1 ? level applied to the bus match select (bm) pin will enable whether byte or word bus width operation on the right port i/os depending on the logic level applied to the size pin. the level of bus match select (bm) must be static throughout normal device operation. the bus size select (size) pin selects either a byte or word data arrangement on the right port when the bus match select (bm) pin is high. a logic ? 1 ? on the size pin when the bm pin is high selects a byte bus (9-bit) data arrangement. a logic ? 0 ? on the size pin when the bm pin is high selects a word bus (18-bit) data arrangement. the level of the bus size select (size) must also be static throughout normal device operation. the big endian select (be) pin is a multiple-function pin during word or byte bus selection (bm = 1). be is used in big endian select mode to determine the order by which bytes (or words) of data are transferred through the right data port. a logic ? 0 ? on the be pin will select little endian data sequencing ar- rangement and a logic ? 1 ? on the be pin will select a big endi- an data sequencing arrangement. under these circumstanc- es, the level on the be pin should be static throughout dual- port operation. long-word (36-bit) operation bus match select (bm) and bus size select (size) set to a logic ? 0 ? will enable standard cycle long-word (36-bit) opera- tion. in this mode, the right port ? s i/o operates essentially in an identical fashion to the left port of the dual-port sram. how- ever no byte select control is available. all 36 bits of the long- word are shifted into and out of the right port ? s i/o buffer stag- es. all read and write timing parameters may be identical with respect to the two data ports. when the right port is configured for a long-word size, big- endian select (be) pin has no appli- cation and their inputs are ? don ? t care ? [44] for the external user. cy7c09569v cy7c09579v ram array ____________ ______________ _______ address read-back figure 1. counter operation diagram 9 / be cy7c09569v cy7c09579v 16k/32kx36 dual port bm size 9 / 9 / 9 / x9, x18, x36 / us mode x36 / figure 2. bus match operation diagram note: 44. even though a logic level applied to a ? don ? t care ? input will not change the logical operation of the dual-port, inputs that are temporarily a ? don ? t care ? (along with unused inputs) must not be allowed to float. they must be forced either high or low.
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 26 of 30 word (18-bit) operation word (18-bit) bus sizing operation is enabled when bus match select (bm) is set to a logic ? 1 ? and the bus size select (size) pin is set to a logic ? 0. ? in this mode, 18 bits of data are ported through i/o 0r ? 17r . the level applied to the big endian (be) pin determines the right port data i/o sequencing order (big endi- an or little endian). during word (18-bit) bus size operation, a logic low applied to the be pin will select little endian operation. in this case, the least significant data word is read from the right port first or written to the right port first. a logic ? 1 ? on the be pin during word (18-bit) bus size operation will select big endian opera- tion resulting in the most significant data word being trans- ferred through the right port first. internally, the data will be stored in the appropriate 36-bit lsb or msb i/o memory loca- tion. device operation requires a minimum of two clock cycles to read or write during word (18-bit) bus size operation. an internal sub-counter automatically increments the right port multiplexer control when little or big endian operation is in effect. byte (9-bit) operation byte (9-bit) bus sizing operation is enabled when bus match select (bm) is set to a logic ? 1 ? and the bus size select (size) pin is set to a logic ? 1. ? in this mode, 9 bits of data are ported through i/o 0r ? 8r . big endian and little endian data sequencing is available for dual-port operation. the level applied to the big endian pin (be) under these circumstances will determine the right port data i/o sequencing order (big or little endian). a logic low applied to the be pin during byte (9-bit) bus size operation will select little endian operation. in this case, the least significant data byte is read from the right port first or written to the right port first. a logic ? 1 ? on the be pin during byte (9-bit) bus size operation will select big endian operation resulting in the most significant data word to be transferred through the right port first. internally, the data will be stored in the appropriate 36-bit lsb or msb i/o memory location. device operation requires a minimum of four clock cycles to read or write during byte (9- bit) bus size operation. an internal sub-counter automatically increments the right port multiplexer control when little or big endian operation is in effect. when transferring data in byte (9- bit) bus match format, the unused i/o pins (i/o 9rq ? 35r ) are three-stated.
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 27 of 30 ordering information 16k x36 3.3v synchronous dual-port sram speed (mhz) ordering code package name package type operating range 100 cy7c09569v-100ac a144 144-pin thin quad flat pack commercial cy7c09569v-100bbc bb172 172-ball ball grid array (bga) commercial 83 cy7c09569v-83ac a144 144-pin thin quad flat pack commercial cy7c09569v-83bbc bb172 172-ball ball grid array (bga) commercial 67 cy7c09569v-67ac a144 144-pin thin quad flat pack commercial cy7c09569v-67bbc bb172 172-ball ball grid array (bga) commercial 32k x36 3.3v synchronous dual-port sram speed (mhz) ordering code package name package type operating range 100 CY7C09579V-100AC a144 144-pin thin quad flat pack commercial cy7c09579v-100bbc bb172 172-ball ball grid array (bga) commercial 83 cy7c09579v-83ac a144 144-pin thin quad flat pack commercial cy7c09579v-83ai a144 144-pin thin quad flat pack industrial cy7c09579v-83bbc bb172 172-ball ball grid array (bga) commercial cy7c09579v-83bbi bb172 172-ball ball grid array (bga) industrial 67 cy7c09579v-67ac a144 144-pin thin quad flat pack commercial cy7c09579v-67bbc bb172 172-ball ball grid array (bga) commercial
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 28 of 30 package diagrams 144-pin plastic thin quad flat pack (tqfp) a144 51-85047-a
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 29 of 30 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagrams (continued) 172-ball bga bb172 51-85114
cy7c09569v cy7c09579v document #: 38-06054 rev. ** page 30 of 30 document title: cy7c09569v/cy7c09579v 3.3 16k/ 32k x 36 flex36 ? synchronous dual-port static ram document number: 38-06054 rev. ecn no. issue date orig. of change description of change ** 110213 12/16/01 szv change from spec number: 38-00743 to 38-06054

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